Effective High-Level Synthesis Design Space Exploration through a Novel Cost Function Formulation
Yiheng Gao, Benjamin Carrión Schäfer · 2021
High-Level Synthesis (HLS) allows to synthesize untimed behavioral descriptions into efficient RTL descriptions (Verilog or VHDL). One key advantage of HLS is that it allows to generate different micro-architectures from the same behavioral description by simply specifying different mixes of synthesis options. These include, how to synthesize arrays (e.g. RAM or registers), loops (unroll completely, partially or not unroll or pipeline) and functions (inline or not). Ideally, the designer would like to find a mix that leads to the smallest and fastest microarchitecture. However, these design parameters are conflicting which means that there is not a single optimal solution but a range of solutions that form a Pareto-front. Out of all the possible synthesis combinations, the most important ones are the ones that lead to Pareto-optimal micro-architectures that form this front. Thus, automatic HLS design space exploration methods are desirable to efficiently find these micro-architectures automatically. This work investigates how formulating the cost function affects the quality of the exploration and its runtime and proposes a new cost function that leads to better results compared to the traditional formulation based on weighted-sum of the design metrics. We show that the newly proposed cost function leads to better results for three well-known meta-heuristics. In particular simulated annealing, genetic algorithm and ant-colony optimization.