PositGen-A Verification Suite for Posit Arithmetic
Annarao Kulkarni, Shashikala Pattanshetty, Aneesh Raveendran, David Selvakumar, Sandra Jean, Vivian Desalphine · 2021
Typically verification of arithmetic units is based on simulation/emulation with random / coverage models enabled constrained test vectors or formal techniques. Our PositGen generates coverage models based Posit domain vectors, enabling a native PositIn and PositOut verification paradigm for Posit units covering corner and special cases. It generates vectors for Add, Sub, Mul, Fused Multiply Add/Sub (FMA/S), Div., Sq. Root and data conversion. As a case study, test vectors have been generated for Posit (16, 1) and (32, 2) and adopted for verifying Posit Add/Sub, FMA/S, Div. and Sq. root units with functional simulation. Further, Posit units have been verified with randomly generated vectors (random integers plugged to regime, exponent, fraction parts of (16, 1), (32, 2)). Besides, FPGen and Berkeley Test Float vectors for IEEE-754 single precision (SP) floating point arithmetic has been mapped to Posit (16,1) and (32, 2) and adopted as another kind of vectors. Code coverage analysis has been done for all the above three approaches. SoftPosit library is the reference for outputs. Irrespective of type of operations, PositGen provides wider coverage on Focused Expression Coverage (FEC) conditions and expressions as compared to Random models and IEEE-754 to Posit convert vector based approaches.