Design and Evaluation of a FIR Filter Using Hybrid Adders and Vedic Multipliers
Juthi Farhana Sayed, Bhuiyan Hasibul Hasan, Babul Muntasir, Mehedi Hasan, Farhadur Arifin · 2021 2nd International Conference on Robotics, Electrical and Signal Processing Techniques (ICREST) · 2021
In this paper, FIR filter of 45nm technological node has been presented, which is a basic filter in DSP applications. Hybrid Adder has been introduced to improve cost and power consumption of the circuit. A Vedic multiplier and D-type register have also been introduced in the proposed FIR filter. 2-bit 4 tap direct and transposed form of FIR filter have been designed for computational data comparison. Results show that the hybrid adder design has almost 6 times lower power consumption than our conventional Adder using complementary CMOS logic. The smaller number of Delay elements of direct-from FIR further reduces power consumption, area and transistor numbers. Therefore, by using our circuits, the overall performance and power consumption of FIR filter has been improved significantly. To implement the circuits, DSCH software has been used and to design the layout, Microwind has been used.