Design and Power Analysis of 32-Bit Pipelined Processor
Aadarsh Aadarsh, Aditya Kumar, Aditya Yadav, P. C. Joshi · 2021 International Conference on Advance Computing and Innovative Technologies in Engineering (ICACITE) · 2021
The system which is proposed here is an advanced solution for the application of MIPS 32-bit Processor at a particular place. The technology used behind this project is Clock Gating achieved in Xilinx ISE Design Suite 14.2 software which is a well-organized and advanced solution for saving design & verification time. This project was developed to produce a prototype product low power-based MIPS 32-bit processor that allows user to calculate the power of the working processor. The monitoring is that this prototype system that allows user to continuously monitor the real time power consumed and CPU processing time. This project is divided into the different modules like ALU (ADD, SUBSTRACT, AND, OR), DATA MEMORY, INSTRUCTION MEMORY, CLOCK Generation. This is done by designing the processor hierarchy.