Configurable Address Computation in a Parallel Memory Architecture
Eero Aho, Jarno Vanne, Kimmo Kuusilinna, Timo D. Hämäläinen, Jukka P. P. Saarinen · 2001
Abstract:- Implementation of an address computation unit for a configurable parallel memory architecture is presented. The benefit of configurability is that a multitude of access formats and module assignment functions can be used with a single hardware implementation, which has not been possible in prior embedded parallel memory system. In addition to design and implementation, a simulation example is given for an image processing application. Results show significant reduction in the overall memory accesses, which is the key to solve the processor-memory bottleneck. Key-Words: configurable parallel memory, address computation, conflict free access, module assignment function, page table