High-Throughput Polynomial Multiplier Architecture for Lattice-Based Cryptography
Taishin Shimada, Makoto Ikeda · 2021
We propose a polynomial multiplier for lattice-based cryptography that achieves a throughput of 24.2 times higher than the state-of-the-art design. We have optimized the proposed architecture for ASIC implementation, instead of FPGA or CPU implementation. We employed shift register to reorder values to avoid complex memory accesses, and we realize complete pipeline operation for higher throughput. Also, we show that raising the degree of parallelism in this design increases throughput per area. This work will lead to the acceleration of Ring-LWE and Module-LWE-based cryptography, which attracts much attention for its resistance to quantum computers and applications in fully homomorphic encryption (FHE).