Integrated Circuit Design of an Improved Discrete Chaotic Map by Averaging Multiple Seed Maps
Md Sakib Hasan, Partha Sarathi Paul, Maisha Sadia, Md Razuan Hossain · 2021
In this paper, a novel method is proposed to build an improved 1-D discrete chaotic map circuit by averaging the output of multiple seed maps. The design is done in a 65 nm CMOS process and is applicable to other technology nodes as well. We show the results for two and three seed maps but the general scheme is compatible with any number of seed maps. The chaotic properties are evaluated using the bifurcation diagram, Lyapunov exponent, Shannon entropy and correlation coefficient. We have found that by having a suitable combination of seed maps, the proposed averaging scheme has a much wider chaotic range with better chaotic performance than constituent seed maps. This can be useful for many applications such as reconfigurable logic gate, chaos-based cryptography, side-channel attack mitigation, random number generation, and so on, where a robust and wide chaotic range is desired.