HW/SW approaches for RISC-V code size reduction
Matteo Perotti, Pasquale Davide Schiavone, Giuseppe Tagliavini, Davide Rossi, Tariq Kurd, Hill, Mark, Yingying, Liu, Luca Benini · Repository for Publications and Research Data (ETH Zurich) · 2020
Code density is a significant concern for low-cost IoT MCUs, as it directly impacts the on-chip memory area (and cost) and indirectly influences power and performance.Even though RISC-V features a compressed ISA, the size of RISC-V binaries is often larger, on several benchmarks, than that of the incumbent MCU ISA.In this paper, we provide a deeper insight into how the ISA design, together with the SW environment, influences RISC-V code density, and we explore several approaches to improve it.First, we explain how to tune the toolchain at compile-and link-time with optimal settings, including those needed for including libraries and using the linker script.Second, we demonstrate that RISC-V non-standard extensions, such as the Xpulp extension, can boost performance without any code size penalty.Finally, we propose a new RISC-V ISA extension that explicitly targets improved code density, with a special focus on the push/pop instructions, needed to handle multiple stack memory operations.The extension effectively reduces the code density gap, both on the Embench open benchmark (from 11.8% to 7.7%) and also on 3GPP industry-strength code aimed at enabling low power, low data rate machine-to-machine communication (from 11.5% to 5.8%).Finally, we provide an implementation of the ISA extension on the open CV32E40P core to evaluate the impact on the core area and operating frequency.Results show a minimal increase of 2.5% of the core area and no impact on the maximum frequency.