An Automated Traffic Generation Framework for Performance Evaluation of Networks-on-Chip for Real World Use Cases
Sri Harsha Gade, Anup Gangwar, Ambica Prasad, Nitin Kumar Agarwal, Ravishankar Sreedharan · 2021
Networks-on-Chip (NoCs) are fast becoming the defacto interconnection fabric for System-on-Chip (SoC) architectures. Early stage performance modeling is a critical step in NoC design for design space exploration and achieving efficient topologies within Time-To-Market (TTM) demands. In this paper, we propose an automatic traffic generation framework for early and comprehensive analysis of NoCs. Using behavioral input and five independent control parameters, it generates a wide range of spatio-temporal traffic stimuli, including bursty traffic while honoring all design constraints. Generated profiles include use-case scenarios representative of actual SoC traffic and plethora of scenarios for out-of-bound performance analysis. Evaluation on production level SoCs shows that the profiles generated are within 5% margin of actual traffic, enables quick iterations from early stages and shrinks TTM from months to few weeks. Final evaluation using RTL testbenches meets performance in all cases.