Performance Evaluation of Unrolled Cipher based Glitch PUF Implemented on Virtex-7
Yusuke Nozaki, Shu Takemoto, Yoshiya Ikezaki, Masaya Yoshikawa · 2021
As security technology for the IoT, the physically unclonable functions (PUFs) have attracted attention. The unrolled cipher PRINCE based glitch PUF (PG PUF) has been proposed for a lightweight application. The PUF is affected by the process rule because PUF utilizes small manufacturing variation; therefore, the evaluation with the different process rules is very important. This study evaluates PUF performance of PG PUF implemented on 28nm process FPGA Virtex-7. Experimental results showed that the results of 28nm process FPGA became worse compared with that of 65nm process. This study also showed the range setting of glitch generator according to the different process rules was important.