Design of a 16-Bit Posit Multiplier with Power Efficiency
Monisha. R · International Journal for Research in Applied Science and Engineering Technology · 2021
Considering the many number of arithmetic functions or operations existing till now, we deem multiplication to be one of the most utilized function.They are implemented in various fields.Most notable applications are signal processing, graphics and scientific computation.Posit number system is widely used nowadays in replacement for IEEE number system.In this paper, we propose the architecture of a 16 -bit modified posit multiplier, which results in less power consumption.In the posit multiplier, our work relates to the mantissa multiplier.The multiplier used for mantissa is structured mainly for providing maximum bit-width that is possible, where the entire multiplier can be partitioned to produce smaller multipliers.Only the necessary partitioned multipliers will be used during the time of execution.Thus resulting in less power consumption.