PMCNOC: A Pipelining Multi-Channel Central Caching Network-on-Chip Communication Architecture Design
Nan Wang, Azeez Sanusi, Peiyi Zhao, Shaheen Mohamed, Magdy Bayoumi · SiPS ... design and implementation - IEEE Workshop on Signal Processing Systems · 2007
As technology scales toward deep submicron, the integration of a large number of IP blocks on the same silicon die is becoming realistic. Network-on-chip (NOC) architectures have been recently proposed as a promising solution for the increasing complex on-chip communication problems. This paper presents a new NOC switch architecture, Pipelining Multi-channel Central Caching NOC (PMCNOC) to offer an efficient way to increase the system throughput and reduce communication latencies. The problem of head-of-lines and deadlocks has been significantly alleviated. We have shown through experimentation that the new proposed architecture not only exhibits hardware simplicity, but also significantly increases overall system performance.