HIGH SPEED AND AREA EFFICIENT VLSI IMPLEMENTATION ON REAL VALUED FFT STRUCTURES
G.Siva, M.Adiseshaiah, Dr.P.Krishna Murthy · Journal of Emerging Technologies and Innovative Research · 2021
Efficient computation of real-valued fast Fourier transform (RFFT) has received significant attention in recent years due to its several applications in conventional digital signal processing and other emerging areas. In-place RFFT architectures are gaining popularity due to their lower hardware complexity compared with pipeline architectures. In previous method, a design approach is presented to develop an area-delay and energy-efficient architecture for in-place RFFT. Generally, an in-place fast Fourier transform (FFT) structure consists of a butterfly block which performs a set of butterfly operations in every clock cycle. The resolution of memory access conflict is however more challenging for higher butterfly block sizes. Therefore, we have analyzed the data-flow and memory footprint of in-place RFFT architectures for different throughput requirements, and based on that, we have proposed here a strategy to partition the storage unit into several banks of smaller sizes (without increasing the overall memory size) to resolve the memory access conflicts by concurrent data-swapping between the banks. In this paper ,we have designed a new butterfly unit is proposed in which 8 point butterfly unit is implemented by two 4 point FFT unit with simple butterfly structure and low memory requirement. so when compare to the previous method the proposed method consume less area over ahead and less delay. The synthesis and simulation results are verified by using Xilinx ISE 14.7 tool.