Design and Implementation of an Instruction Set Architecture and an Instruction Execution Unit for the REZ9 Coprocessor System
Daniel Spencer Anderson · Digital Scholarship - UNLV (University of Nevada Reno) · 2020
While the use of RNS has provided groundbreaking theory and progress in this field, the applications still lack viable testing platforms to test and verify the theory. This Thesis outlines the processing of developing an instruction set architecture (ISA) and an instruction execution unit (IEU) to help make the first residue based general processor a viable testing platform to address the mentioned problems. Consider a 32-bit ripple adder. The delay on this device will be 32N where N is the delay for each adder to complete its operation. The delay of this process is due to the need to propagate each carry signal generated by each adder to the next one. This was solved by the creation of the Carry Look Ahead (CLA), which could drastically reduce the delay by 2/3. However, like the ripple adder, the CLA is still encumbered by propagation delay. A residue processor in the same situation would have a delay of 1N regardless of bit size since carry propagation is no longer a concern. The Thesis discusses how prior challenges using residue number systems in computers has been overcome by Digital System Research (DSR).