The Plural Many‐core Architecture – High Performance at Low Power
Ran Ginosar · 2021
The Plural many-core architecture combines multiple CPU cores, hardware scheduling and a large on-chip shared memory. The Plural PRAM-like programming model is based on non-preemptive execution of multiple sequential tasks. The Plural architecture specifies two specialized networks-on-chip (NoCs), one connecting the scheduler to all cores and other schedulable entities (DMA controllers and hardware accelerators) and a second NoC connecting all cores and other data sources (DMA controllers) to the shared memory. The Plural architecture offers two solutions: on-chip and off-chip hardware accelerators. The architecture is shown to be highly efficient for signal processing and machine learning applications, both based on simple linear algebra operators that exhibit high levels of data parallelism. The chapter also presents a Plural algorithm for matrix–matrix multiplication.