A partitioning algorithm for system-level synthesis
Menez, Auguin, Boeri, Carriere · IEEE/ACM International Conference on Computer-Aided Design · 1992
The partitioning/scheduling/allocation algorithm developed for the CAPSYS method is presented. The aim of this project is to define a tool able to automatically design dedicated and embedded VLIW architectures for large and complex applications. It inherits a sizable knowledge-pool from the wider field of parallel processors, VLIW compiler design and high-level synthesis. Emphasis is placed on constraints of such a system synthesis approach and more especially on the particularity of the partitioning step. The proposed solution implements a software/hardware approach based on the list-scheduling heuristic.>