The Design and implementation of parallel processing system using the $Nios^{(R)}$ II embedded processor
Sihyun Lee · Journal of the Korea Society of Computer and Information · 2009
In this thesis, we discuss the implementation of parallel processing system which is able to get a high degree of efficiency(size, cost, performance and flexibility) by using II(32bit RISC(Reduced Instruction Set Computer) processor) embedded processor in DE2- reference board. The designed Parallel processing system is master-slave, shared memory and MIMD(Mu1tiple Instruction-Multiple Data stream) architecture with 4-processor. For performance test of system, N-point FFT is used. The result is represented speed-up as follow; in the case of using 2-processor(core), speed-up is shown as average 1.8 times as 1-processor's. When 4-processor, the speed-up is shown as average 2.4 times as it's.