Automatic design for bit-serial MSPA architecture
Hiroaki Kunieda, Yusong Liao, Dongju Li, K. Ito · 2002
A memory sharing processor array (MSPA) architecture is effective in both data storage and processor cell utilization efficiency. In this paper, the design methodology for MSPA is extended to synthesise a bit-serial datapath. As a synthesis example, we propose a new bit-serial multiplier with a smaller number of logic gates than conventional bit-serial multipliers.