Design of high-performance polar codes decoders for wireless communication
ChenYang Xia · 2020
As the first kind of forward error correction (FEC) codes that achieve channel capacity, polar codes have attracted much research interest recently. They have been selected as one of the coding schemes for the 5G wireless communication networks and are competitive candidates for future communication standards due to the excellent error-correction performance. The traditional polar codes discovered by Arikan are decoded by successive-cancellation (SC) decoding, which provides a sub-optimal decoding performance for short polar codes adopted in 5G communication, and their code lengths are restricted to an integer power of 2. Various research work has been done to solve these issues. To improve the error-correction performance, successive-cancellation list (SCL) decoding with cyclic redundancy check (CRC) was proposed. A large list size is necessary for SCL decoding to achieve low error rate at a low signal-to-noise ratio (SNR). To improve the flexibility on code length, multi-kernel (MK) polar codes have been proposed, which support code lengths other than an integer power of 2. In this thesis, the decoding algorithms are optimized for the design of high-performance hardware architectures of polar codes decoders. First, a high-throughput implementation of SCL decoding with a large list size is studied. Polar codes decoded by SCL decoding with a large list size have better error-correction performance compared with other popular FEC codes. However, due to the serial decoding nature of SCL decoding and the high complexity of list management, the decoding latency is high, which limits the usage of polar codes in practical applications that require low latency and high throughput. To solve these problems, at the algorithmic level, to achieve a low decoding latency with moderate hardware complexity, two decoding schemes, a multi-bit double thresholding scheme (MB-DTS) and a partial G-node look-ahead (P-GLAH) scheme, are proposed. Then, a high-throughput very-large-scale integration (VLSI) architecture implementing the proposed algorithms is developed with optimizations on different computation modules. From the implementation results on UMC 90 nm complementary metal‒oxide‒semiconductor (CMOS) technology, the proposed architecture achieves decoding throughputs of 1.103 Gbps, 977 Mbps and 827 Mbps when the list sizes are 8, 16 and 32, respectively. Second, to further improve the throughput and energy consumption of SCL decoding, a two-stage adaptive SCL (TA-SCL) decoding scheme is studied. Despite its adaptive nature, a TA-SCL decoding has constant system latency and data rate under different channel conditions. A mathematical model based on the Markov chain is developed to explore the trade-off among error-correction performance, decoding speed and hardware complexity for implementing practical designs. A VLSI architecture implementing the TA-SCL decoding is proposed for high decoding throughput and low energy consumption. The proposed architecture is realized using UMC 90 nm CMOS technology. With error-correction performance and hardware complexity similar to those of a conventional SCL decoder of list size 32, the TA-SCL decoder achieves a throughput of 2.35 Gbps and energy consumption of 302 nJ/frame at a block error rate (BLER) of 10‒4, which is a 2.83x improvement and 91% reduction, respectively, compared with the conventional design. Third, to improve the error-correction performance of length- flexible polar codes with low computational complexity, an MK polar code construction method called kernel substitution (KS) is studied. Different from traditional polar codes that are constructed based on a size-2 kernel, MK polar codes are constructed based on kernels with different sizes, and hence they support code lengths other than an integer power of 2. However, the error-correction performance is not as good as those of other existing approaches to flexible code lengths. In this work, we propose an MK polar codes construction method based on a KS scheme to improve its error-correction performance. Simulation results show that 0.15~0.25dB performance gain can be achieved at a BLER of 10‒4 without any computational complexity overhead. An SC decoder architecture for this kind of codes is then proposed and implemented on TSMC 65nm technology. Synthesis results show that the throughput is higher than those of the decoders for other length-flexible polar codes.