Cache coherence in systems with parallel communication channels and many processors
John C. Willis, Arthur C. Sanderson, Christopher Robert Hill · 2002
The authors describe and analyze two algorithms for maintaining cache coherence in multiprocessor systems with parallel communication channels and many processors. A distributed link-list relates all cache frames representing the same main memory block. Messages traverse the list to maintain list integrity, exclusive ownership, and consistent values. Memory access semantics are equivalent to a shared memory system without caches. Reference latency, efficiency of memory use, and hardware complexity are moderate and well-bounded. A brief comparison with the Scalable Coherent Interface illustrates some of the design tradeoffs associated with distributed directory algorithms.>