BIT-LEVEL SYSTOLIC ARRAYS FOR DIGITAL CONTOUR SMOOTHING
JAn lasa · 2005
The paper deals with the analysis of bit-level systolic arrays for digital contour smoothing. Procedures for obtaining new bit-level systolic arrays, which improve the already known designs, were suggested. New sy~tol ic arrays proposed on the bit level have a simple structure. They consist of single type cells Ci-bit full adders3, which are separated by i-bit delay elements. They are suitable for the VLS~ i mpl ementati on.