Novel Approaches to Register Transfer Level Debugging and Embedding Representations for Knowledge Base Completion
Neil Veira · TSpace (University of Toronto) · 2019
Register Transfer Level (RTL) debugging has become one of the main bottlenecks of the VLSI design cycle, as current automated debugging tools struggle to handle to the scale of modern designs. Furthermore, automated techniques for knowledge base completion are rapidly approaching the limits of their predictive ability. This thesis addresses some of the barriers to further automating these tasks. First, a new SAT-based debugging algorithm is described which can accelerate the bug search by guiding the SAT solver to prioritize locations that are more likely to be solutions. Two different techniques are proposed to determine a good prioritization. Empirical evaluation shows that the algorithm can find 83% more suspect bug locations in a given amount of time. This thesis also presents two methods to augment knowledge graph embeddings by incorporating supplementary textual data. Experiments show that both methods lead to improved performance on standard knowledge completion tasks in the majority ofcases.