An H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic voltage/frequency scaling
T. Fujiyoshi, Shinichiro Shiratake, Shuou Nomura, Takafumi Nishikawa, Yoshiyuki Kitasho, Hideho Arakida, Yuji Okuda, Y. Tsuboi, Mototsugu Hamada, Hiroyuki Hara, Takeshi Fujita, Fumitoshi Hatori, Takayoshi Shimazawa, K. Yahagi, Hideo Takeda, M. Murakata, F. Minami, Naoyuki Kawabe, T. Kitahara, K. Seta · 2005
A single-chip H.264/MPEG-4 audio/visual LSI for mobile applications with a module-wise dynamic voltage/frequency scaling architecture is described. This LSI operates even during the voltage/frequency transition with no performance overhead by using a dynamic de-skewing system and an on-chip voltage regulator with slew-rate control. The IC consumes 90mW in decoding QVGA H.264 video at 15f/s and MPEG-4 AAC LC audio simultaneously.