At-Speed Testing with Timing Exceptions and Constraints-Case Studies
Dhiraj Kumar Goswami, Kun-Han Hans Tsai, Mark Kassab, Takeo Kobayashi, Janusz Rajski, Bruce Swanson, Darryl Walters, Yasuo Satô, Toshiharu Asaka, Takashi Aikyo · Proceedings - Asian Test Symposium/Proceedings · 2006
In order to generate correct at-speed scan patterns, the effect of timing exceptions and constraints needs to be considered during test generation. A path-oriented approach to handle timing exception paths during at-speed ATPG has been presented in (Vorisek et al., 2006). The new method has been applied to and tested on many example circuits at Semiconductor Technology Academic Research (STARC). This paper presents a sample of these test cases, and illustrates how the proposed method generates correct-by-construction at-speed patterns on these circuits without pessimism