A processor architecture for Horizon
M.R. Thistle, B.J. Smith · 2003
Horizon is a scalable shared-memory multiple-instruction-stream-multiple-data-stream computer, currently under study, composed of a few hundred identical scalar processors and a comparable number of memories, sparsely embedded in a three-dimensional nearest-neighbor network. Each processor has a horizontal instruction set that can perform up to three floating-point operations per cycle without resorting to vector operations and will be capable performing at a rate of several hundred MFLOPS (millions of floating-point operations per second), to achieve an overall system performance target of 100 GFLOPS (billion of FLOPS). The architecture of the processor in the Horizon system is described.>