Test generation for delay faults in non-scan and partial scan sequential circuits
Kwang-Ting Tim Cheng · IEEE/ACM International Conference on Computer-Aided Design · 1992
A recently proposed transition fault model for sequential circuits is considered. In this fault model, a transition fault is characterized by the fault site, the fault type and the fault size. It was observed that neither a comprehensive functional verification sequence nor a sequence with a high stuck-at fault coverage gives a high transition fault coverage for sequential circuits. Deterministic test generation for delay faults is required to raise the coverage to a reasonable level. Here, a test generation algorithm for this fault model is presented. With the use of a fault injection technique, tests for transition faults can be generated by using a stuck-at fault test generation algorithm with some modifications. The test generator DATEST has been integrated with a sequential circuit delay fault simulator, TFSIM. Experimental results for ISCAS-89 benchmark circuits and some designs are presented. For partial scan circuits, a test application scheme for detecting transition faults is described. Modifications on test generation and fault simulation algorithms required for partial scan circuits are presented. Experimental results are presented.>