A system-level power-estimation methodology based on ip-level modeling, power-level adjustment, and power accumulation
Masafumi Onouchi, T. Yamada, Katsumi Morikawa, Ichiro Mochizuki, Hidetoshi Sekine · Asia and South Pacific Conference on Design Automation, 2006. · 2006
We have developed a specialized rapid power-estimation methodology for multimedia applications. This methodology has adequate accuracy for the first design of a complicated SoC. For a multimedia application, we developed three methodologies: an IP-level modeling, a power-level adjustment methodology, and a power accumulation methodology. With these methodologies, the system-level power estimation on a SoC executing a practical application becomes so precise and easy that we can revise the SoC design to reduce its power. According to a comparison of the system-level power estimated with these methodologies to board-measured power, the error between the two powers is less than 5.6%.