Ravel: assinged-delay compiled-code logic simulation
Shriver, Sakallah · IEEE/ACM International Conference on Computer-Aided Design · 1992
Ravel, a long- and short-path delay-accurate compiled-code logic gate simulator suitable for both the functional and timing verification of multiphase synchronous circuits, is described. It is based on a waveform model of synchronous operation and an associated algebra for combining such waveforms both logically and temporally. This algebra extends the range of compiled-code simulation, which has been limited in the past to static functional verification, so that dynamic signal propagation effects can be captured accurately. For synchronous circuits exhibiting significant event activity per clock cycle, Ravel simulation can be faster than traditional event-driven simulation with no sacrifice in the delay modeling accuracy. Initial experiments with Ravel on a subset of the ISCAS 89 sequential benchmarks confirm its viability as an alternative to event-driven simulation.>