Implementation of Wormhole Router With Low Power Buffer Management
U. Saravanakumar, Anil Krishna Galla, R. Arun, Abhishek Prabhu P · SSRN Electronic Journal · 2013
Network-on-Chip (NoC) is an on-chip communication solution in the future System-on-a-Chip (SoC) compelling high performance operation by consuming low power. In this paper, we present a new dynamic power management technique for wormhole router. This power management technique has implemented in the block level of FIFO and CMOS SRAM buffer in the router. The experimental results show that the proposed router using 10T SRAM buffer reduced the power consumption up to 76.16% than conventional router which has FIFO buffer.