Variation-Tolerant, Power-Safe Pattern Generation
V.R. Devanathan, V.R. Devanathan, V.R. Devanathan, V.R. Devanathan, C.P. Ravikumar, C.P. Ravikumar, C.P. Ravikumar, C.P. Ravikumar, Veezhinathan Kamakoti, Veezhinathan Kamakoti, Veezhinathan Kamakoti, Veezhinathan Kamakoti · IEEE Design & Test of Computers · 2007
By generating safe patterns - those that tolerate on-chip variations - this framework avoids false delay test failures. It uses power grid information and regional constraints on switching activity to minimize peak power and optimize the pattern set. Experimental results on benchmark circuits demonstrate the framework's effectiveness.