DFT of the Cell Processor and its Impact on EDA Test Softwar
Louis Bushard, Nathan Chelstrom, Steven Ferguson, Brion Keller · Proceedings - Asian Test Symposium/Proceedings · 2006
This paper describes aspects of the Cell processor DFT and its effects on the EDA software used to process it. The Cell processor is a very complex multi-core design, and the use of high frequency clocks near 4 GHz drove DFT decisions that had significant implications on several levels. The processor had to support Logic BIST, Memory BIST, OPMSR+, SerDes I/O-WRAP as well as traditional scan-based ATPG all using a free-running high-speed clock