Zero skew clock routing in multiple-clock synchronous systems
Khan, Hossain, Sherwani · IEEE/ACM International Conference on Computer-Aided Design · 1992
A clock routing algorithm for two-phase clock systems is presented. The algorithm, which minimizes both intraclock skew and interclock skew, has been implemented on SPARC 1+ in C and has been tested on several industrial benchmarks as well as on randomly generated examples. In particular, the result was tested for a 267 synchronous component circuit at clock rates of 100 MHz. It is significant that this is the first ever result which deals with multiple clock routing with zero skew.>