A scheduling algorithm for synthesis of bus-partitioned architectures
Vasily G. Moshnyaga, Fumiaki Ohbayashi, Kiichiro Tamaru · 2002
Due to efficient interconnect structure and internal parallelism bus-partitioned architectures are very beneficial for sub-micron chip design. This paper presents a new approach for integrated scheduling and interconnect binding of bus-segmented data-paths. Experiments show that the approach provides better results than existing methods and is quite flexible.