Low-Delay FPGA-Based Implementation of Finite Field Multipliers
José Luis Imaña · IEEE Transactions on Circuits & Systems II Express Briefs · 2021
Arithmetic operations over binary extension fields GF(2m) have many important applications in domains such as cryptography, code theory and digital signal processing. These applications must be fast, so low-delay implementations of arithmetic circuits are required. Among GF(2m) arithmetic operations, field multiplication is considered the most important one. For hardware implementation of multiplication over binary finite fields, irreducible trinomials and pentanomials are normally used. In this brief, low-delay FPGA-based implementations of bit-parallel GF(2m) polynomial basis multipliers are presented, where a new multiplier based on irreducible trinomials is given. Several post-place and route implementation results in Xilinx Artix-7 FPGA for different GF(2m) finite fields are reported. Experimental results show that the proposed multiplier exhibits the best delay, with a delay improvement of up to 4.7%, and the second best Area×Time complexities when compared with similar multipliers found in the literature.