Precise timing verification of logic circuits under combined delay model
K Kimura, Kashima, Haneda · IEEE/ACM International Conference on Computer-Aided Design · 1992
A combined delay model to manipulate the variance of the delay time of logic elements and a timing verification method based on the theory of regular expressions are presented. Emphasis is placed on the hazard detection problem and the verification of asynchronous circuits. The effectiveness of the method with medium sized circuits including about 100 elements is shown.>