Enhancing Code Density of Transport Triggered Architecture through dual-mode Computing
Lei He, Xuemi Zhao, Zhiying Wang · Journal of Communication and Computer · 2007
Transport triggered architecture (TTA) processors suffer from poor code density, because the instruction word specifies parallel data transports directly. RISC|TTA dual-mode computing is presented to enhance the code density. RISC can be taken as a heuristic vertical code compression method. Computation-intensive loops, which occupy most of the computing time and have more instruction level parallelism, are performed in TTA mode to get higher performance, and the others are processed in RISC mode to achieve better code density. Experimental results from several benchmarks in DSP Stone show that the code size can be reduced to about 31% of the original TTA program size with 4% performance overheads.