High-Speed C-Testable Systolic Array Design for Galois-Field InversionChih-Tsun Huang and Cheng-Wen Wu
C-T. Huang, Wu Cw · European Design and Test Conference · 1997
Systolic architectures for inversion in Galois field (GF(2^m)) are presented. The proposed inversion algorithm is a counter-free extended Euclidean algorithm, which results in simple circuit implementation for GF inversion. Additionally, the bit-parallel implementation proposed is shown to be C-testable. Testability and modularity make it suited to VLSI implementation.