Design and Implementation of a Multiply-Accumulate (MAC) unit
Neethu Johny, Divya Rajan · Zenodo (CERN European Organization for Nuclear Research) · 2019
This paper studies the data-path and VLSI implementation of multiply accumulate (MAC) unit. MAC unit performs multiplication and accumulation process and is an important operation in many of the digital signal processing (DSP) applications. The multiplier is designed using Wallace multiplier and the adder is designed as a carry look ahead adder. The performance analysis of MAC unit is done in terms of area and delay. The design of the MAC model is done in Verilog HDL. The MAC unit is then simulated and synthesized in Xilinx ISE 14.7 for Artix 7 family and the performance analysis is done in terms of area and delay.