An FPGA-Implemented Parallel System of Face Recognition, for Digital Forensics Applications
Μαρία Παντοπούλου, Nicolas Sklavos · 2020
With the number of crime cases increasing daily, the Digital Forensics sector is growing rapidly. More and more researchers search for efficient face recognition systems, which will provide fast and accurate results in order to uncover crime suspects. Although many software implemented systems exist, they seem to have speed problems. This is the reason why hardware implemented systems are preferred. In this paper, an FPGA hardware implementation is proposed, which processes four images in parallel in order to reduce the total execution time and the on-line training process is applied. The system operates in a frequency of 66.23 MHz and the total execution time is almost 128 ms due to the on-line training. The Yale face database is used and the accuracy of the implemented system is 80% for 30 consecutive trials. The design is performed for an Artix-7 FPGA.