Efficient Identification of Undetectable Two-Cycle Gate-Exhaustive Faults
Irith Pomeranz · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2021
As a superset of cell-aware faults, gate-exhaustive faults provide a target for the generation of a comprehensive test set. Considering two-cycle gate-exhaustive faults, the number of faults can be excessive, and many of the faults are undetectable. This article considers the efficient identification of undetectable two-cycle gate-exhaustive faults. To take advantage of the large numbers of necessary assignments the faults have, the procedure described in this article is based on the computation of input necessary assignments. This article also notes that gates with large percentages of undetectable two-cycle gate-exhaustive faults are more important to target for test generation. Experimental results are presented for such gates in benchmark circuits.