A Systematic Design Methodology of Formally Proven Side-Channel-Resistant Cryptographic Hardware
Rei Ueno, Naofumi Homma, Sumio Morioka, Takafumi Aoki · IEEE Design and Test · 2021
This article proposes a formal design system for automatically generating provably secure register transfer level description of cryptographic hardware based on generalized masking scheme. -Rosario Cammarota, Intel Labs -Francesco Regazzoni, University of Amsterdam and Università della Svizzera Italiana