Automatic Timing Closure for Relative Timed Designs
Tannu Sharma, Kenneth S. Stevens · 2020
Relative timing is a universal representation of the sequencing property of time. Relative timing can be applied to specify the correctness and performance properties of digital circuits in the form of a set of timing constraints. These constraints are passed to commercial synthesis, place and route, and timing verification tools to optimize the robustness, power, and performance of digital integrated circuits. This paper presents an algorithm for the automatic convergence of a set of relative timing constraints in the synthesis and place and route flows to create a timing closed design. The algorithm can perform timing closure for a design starting with zero maximum delay targets. This tool produces improved results compared to a start point with delay values close to final closed values.