A Conflict-Aware Capacity Control Mechanism for Last-Level Cache
Jiaheng Liu, Ryusuke Egawa, Mulya Agung, Hiroyuki Takizawa · 2020
As the number of cores on a processor chip increases, the capacity and the number of levels of the cache hierarchy increases, which causes higher energy consumption of the computing system. However, the usage of a cache hierarchy may vary significantly among applications. Thus, determining an appropriate cache hierarchy for each application is crucial to improve performance and energy efficiency. In this paper, we propose a mechanism to improve energy efficiency by adapting a cache hierarchy to individual applications. First, our mechanism bypasses and disables some of the cache levels if their contributions to performance are small. Then, based on the cache utility, the mechanism optimizes the capacity and associativity of the last-level cache. The experimental results with the PARSEC benchmarks show that the proposed mechanism can improve energy efficiency by 26% and 10%, compared with the baseline and cache-level bypassing mechanisms, respectively.