Multiple-NoC Exploration and Customization for Energy Efficient Traffic Distribution
Sonal Yadav, Vijay Laxmi, Manoj Singh Gaur · 2020
Motivation. As more on-chip computation resources are available, the Networks-on-Chip (NoC) power consumption is expected to increase in the future many-core era. Many of these would have to be switched off while inactive to keep power consumption and chip temperature low. However, the NoC infrastructure must be kept alive to serve shared caches and memory accesses. A recent study shows that the proportion of NoC power consumption becomes appreciable in comparison to computation counterpart. A 32 core chip at 45nm substantially raises NoC power ( ~ 42%) among the remaining on-chip active resources (cores, shared caches, memory controllers, PCIe controllers) [1]. Therefore, low power becomes the primary objective for modern NoC designs.