The Ultimate Data Flow for Ultimate Super Computers-on-a-Chip
Veljko M. Milutinović, Miloš Kotlar, Ivan Ratković, Nenad Korolija, Miljan Djordjevic, Kristy Yoshimoto, Mateo Valero · Advances in systems analysis, software engineering, and high performance computing book series · 2021
This chapter starts from the assumption that near future 100BTransistor SuperComputers-on-a-Chip will include N big multi-core processors, 1000N small many-core processors, a TPU-like fixed-structure systolic array accelerator for the most frequently used machine learning algorithms needed in bandwidth-bound applications, and a flexible-structure reprogrammable accelerator for less frequently used machine learning algorithms needed in latency-critical applications. The future SuperComputers-on-a-Chip should include effective interfaces to specific external accelerators based on quantum, optical, molecular, and biological paradigms, but these issues are outside the scope of this chapter.