Encoder and Adaptive Decoder for a (15,6,2) DEC-TED BCH Code
P A V Krishna Rao, Pranjali Babshet, Ramya Arun Babu, M S Sunita · 2020
In this paper, an encoder and decoder for a double-error-correcting and triple-error-detecting (DEC-TED) (15,6,2) Bose-Chaudhuri-Hocquenghem (BCH) code are implemented for error correction in emerging memories. The encoder converts 6-bit data into 15-bit codewords. Emerging memories have fast read/write access times, and are often used in low-power applications. Hence, an adaptive technique is implemented in the decoder, providing lower power consumption and decoding latency compared to the conventional decoder. It detects the number of errors in a codeword, applies a different error correction algorithm for each error type as necessary, and retrieves error-free data. Its dynamic power consumption is further reduced by stabilizing the glitches that propagate to the error correcting blocks. Implementation was performed using the 28 nm Xilinx FPGA part xc7a35tcpg2361. With only 1.11% increase in FPGA resource utilization, the adaptive decoder achieves 64.4% average power reduction, and 35.68% average latency reduction when compared to the conventional decoder.