Hardware Implementation of Floating Point Matrix Inversion Modules on FPGAs
S Chetan, J. Manikandan, V Lekshmi, S Sudhakar · 2020
Matrices are employed for diversified applications such as image processing, control systems, video processing, radar signal processing, compressive sensing and many more. Finding inverse of a floating point large scale matrix is considered to be computationally intensive and their hardware implementation is still a research topic. FPGA implementation of four different floating-point matrix inversion algorithms using a novel combination of high level language programming and model based design is proposed in this paper. The proposed designs can compute inverse of a floating point matrix up to a matrix size of 25×25 and can be easily scaled to large size matrices. The performance evaluation of proposed matrix inversion modules are carried out by their hardware implementation on a Zynq 7000 FPGA based ZED board and the results are reported.