A Fast and Efficient FPGA-based Level Set Hardware Accelerator for Image Segmentation
Ye Liu, Yin Wang, Liang Juan Chang, Jun Zhou · 2020
Level set algorithm has been widely used for image segmentation due to its high accuracy. In addition, compared to the deep learning-based image segmentation methods, the level set algorithm can be implemented without training data, which significantly reduce the labelling efforts. However, the normal level set algorithm is still developed using software, involving complex computation with a large number of pixels and iterations. Also, the software implementation induces long processing time and large power consumption. In this work, we propose a FPGA-based level set hardware accelerator for image segmentation. The proposed hardware accelerators contain four design components: task-level parallel processing, image splitting processing, fully-pipelined processing architecture, and time multiplexed gradient and divergence processing engine. Based on the experimental results, our proposed hardware accelerator achieves up to 10.7× acceleration compared to the level set algorithm executing on CPU, with only 2.2 W power consumption.