FPGA based image readout from Camera using Ethernet protocol and Python
Akshay Augustine, Anand P, K. Devadershan, K. Udaya Kiran, P Kiran, Bhuvan Balan · 2020
This paper presents the design and development of a prototype model of an FPGA based pixel data readout from a camera to a host system (PC). An Artix-7 series FPGA on the NEXYS4-DDR board acts as the main controlling unit between the image sensor and the PC. Ethernet mode of communication is used for transferring the image data from the FPGA to the host system. A Python application is developed for reading and visualizing the image from the Ethernet data received in the host system. Besides facilitating the data transfer between the image sensor and the host PC, the FPGA includes various blocks needed for testing and debugging. Using these blocks, the image readout system is designed in a lab-access limited environment. The image sensor operates at 25 MHz with a spatial resolution of 640 x 480 and a temporal resolution of 30 fps.