On-chip Interconnect Optimization and Validation using Virtual Platform
Jungyun Choi, Kyungsu Kang, Sang‐Ho Park, Seunghan Lee, Yohan Park, Byeongwook Bae, Byunghoon Lee, ByungChul Yoo · 2020
As today's multi-media applications require higher performance, the complexity of data-path including on-chip interconnect and memory sub-system is increasing more. In this paper, we propose ISA (Interconnect Simulation Analysis) which automatically generates a virtual platform and verify the data path performance. Since ISA uses DUT (Design under Test), it gives 100% performance accuracy. In addition, ISA supports slaves from both SystemC Model and RTL11In this paper, RTL means a hardware description language with register-transfer level such as Verilog or VHDL., Design/Verification Engineer can optimize the design of interconnect efficiently. Experimental results show that ISA help reduce power and area while meeting the target performance.